Recent density increase in electronic devices has accelerated multilayering of a circuit board used in these devices such as a flexible printed circuit board. A build-up method is generally employed for laminating such a multilayer circuit board. A build-up method refers to a method for forming interlayer connection between monolayers while piling up resin layers made of a resin alone and conductor layers.
The build-up methods can be generally categorized into those where a via hole is formed in resin layers before forming an interlayer connection and those where an interlayer connection is formed before laminating resin layers. Methods for forming an interlayer connection are categorized into formation of a via hole by plating and formation using a conductive paste.
There has been disclosed a technique allowing for stacked-via and density increase and simplification of an interconnection design, wherein a fine via hole for interlayer connection is formed in a resin layer by laser and the via hole is filled with a conductive adhesive such as a copper paste, by which electric connection is formed (for example, see Japanese Laid-open Patent Publication No. 1996-316598).
However, the above method may not provide adequately reliable interlayer electric connection because the connection is formed via a conductive adhesive. Furthermore, the method requires an advanced technique for filling a fine via hole with a conductive adhesive and thus cannot cope with further miniaturization of an interconnection pattern.
Thus, instead of filling a via hole with a conductive adhesive, there has been employed a technique where a metal protrusion (a conductor post) is used. However, even in a case where a conductor post is used, there has been disclosed a method where while forming an interlayer connection, a conductor post physically removes an interlayer adhesive for forming connection with a conductor pad (for example, see Japanese Laid-open Patent Publication No. 1999-54934).
However, this method cannot completely remove the interlayer adhesive between the conductor post and the conductor pad, which may lead to inadequately reliability.
Alternatively, there has been proposed a method wherein using the above conductor post with a solder layer on the tip, the conductor post penetrates an uncured resin layer and an uncured adhesive layer at a temperature lower than a melting point of the solder, and then the conductor pad is pressed at about 2.5 MPa, and then the adhesive layer is cured and then the solder is fused and cooled to form a solder bonding (for example, see Japanese Laid-open Patent Publication No. 1996-195560).
However, such manufacturing a circuit board by forming interlayer connection by compression may lead to phenomena such as distortion in an internal layer circuit and corrugation of a circuit board due to distortion of an internal layer circuit. In particular, there is a tendency that the larger number of piled internal circuits leads to more significant distortion or corrugation.
Patent Document 1: Japanese Laid-open Patent Publication No. 1996-316598
Patent Document 2: Japanese Laid-open Patent Publication No. 1999-54934
Patent Document 3: Japanese Laid-open Patent Publication No. 1996-195560